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What Is A Full Adder / Creating A Single Bit Full Adder?
Written By: Kia Javadi

The purpose of this article is to introduce an essential component to binary computation - a full adder.  For simplification the single bit full adder will be considered (from which the device can be scaled to multiple bits).  This article also touches upon layout design and sizing considerations with regard to power optimization principles. Input-to-Sum and Carry-in to Carry-out timing restrictions are also factored into this sizing consideration.

What Is A One-Bit Full Adder...

A one-bit full adder is a device with three single bit binary inputs (A, B, Cin) and two single bit binary outputs (Sum, C-out). Having both carry in and carry out capabilities, the full adder is highly scalable and found in many cascaded circuit implementations.

The basic logic functions of the full adder can be summarized in the truth table (right). From the truth table it can be seen that the full adder can be trivially constructed with two half adders. The full adder can also be decomposed into the following logical relationships:




One possible implementation of the full adder is the Mirror Full Adder. This circuit device consists of 28 total transistors (4 transistors used for the construction of two inverters). Since the full adder acts as a fundamental building-block component to larger circuits units, timing and power consumption optimization efforts at the adder level can lead to improved circuit throughput ratings, enhanced speed performance, and lowered power consumption requirements.  Thus at this fundamental level it is very important to minimize latency and resolve any timing issues in order to avoid issues inevitably brought about by scaling.

Sizing and Power Optimization Considerations...

While there are many possible techniques to use in the transistor optimization process - buffering, size progression, ordering, etc. – the most effective means by which propagation delay and power consumption can be minimized comes with the sizing of the transistors. With sizing modifications, one could alter the resistive characteristics of the transistor to decrease the time delay through the device (t ~ R*C) and effectively increase its current drive capabilities. This technique has been used extensively in the commercial industry with an example coming in Intel’s modification of their Northwood core (.13-micron process) to their newly released Prescott core (.09-micron process). Other changes that can be made come in the setting of VDD, which can be increased to boost speed or decreased to improve power conservation, and the operational clock frequency, which when lowered can greatly improve power consumption losses. In making modifications, however, it is important to understand the many tradeoffs that also occur. With sizing, these manifest as introduced parasitic capacitances that can act against the optimization gains. Thus, the effective goal in design comes not only in improving upon a measurement, but rather, reaching a point at which the net benefit at a maximum.

Full Adder Schematic...

Here is one possible implementation for a Full Adder at the transistor level (Mirror Adder):

Sample transistor sizing values for an optimal implementation - .25µm CMOS Process:

Sizing Values 

 

 

 

 

 

 

M1

NMOS

W=1.2876u

L=0.25u

 

M13

PMOS

W=3.6846u

L=0.25u

M2

NMOS

W=1.2876u

L=0.25u

 

M14

PMOS

W=1.5u

L=0.25u

M3

NMOS

W=1.2876u

L=0.25u

 

M15

PMOS

W=3.379u

L=0.25u

M4

NMOS

W=1.2876u

L=0.25u

 

M16

PMOS

W=3.379u

L=0.25u

M5

NMOS

W=1.2876u

L=0.25u

 

M17

PMOS

W=1.5u

L=0.25u

M6

NMOS

W=1.2876u

L=0.25u

 

M18

PMOS

W=1.2876u

L=0.25u

M7

NMOS

W=1.2876u

L=0.25u

 

M19

PMOS

W=1.2876u

L=0.25u

M8

NMOS

W=1.2876u

L=0.25u

 

M20

PMOS

W=1.2876u

L=0.25u

M9

NMOS

W=1.2876u

L=0.25u

 

M21

PMOS

W=1.2876u

L=0.25u

M10

NMOS

W=1.2876u

L=0.25u

 

M22

PMOS

W=1.2876u

L=0.25u

M11

NMOS

W=1.2876u

L=0.25u

 

M23

PMOS

W=1.2876u

L=0.25u

M12

NMOS

W=1.2876u

L=0.25u

 

M24

PMOS

W=1.2876u

L=0.25u

M25

NMOS

W=3.379u

L=0.25u

 

M26

PMOS

W=3.379u

L=0.25u

M28

NMOS

W=1.5u

L=0.25u

 

M27

PMOS

W=1.5u

L=0.25u

Reducing Dynamic Power Consumption...

A great improvement to an adder (or any other scalable device) is the reduction of power consumption.  Power consumption issues can lead to over consumption of resources when devices are cascaded so they must be planned for at the fundamental design level. With respect to VDD (High Voltage), one could greatly reduce the dynamic power consumption of the mirror-cell circuit above by decreasing the supply voltage (Power = CL * I*VDD^2*f). As seen by the formula, the VDD component is squared, indicating a nonlinear reduction in power per voltage reduction in VDD. However, this reduction in power would come at the expense of overall speed and increased delay. In extreme instances in which VDD is greatly reduced, interference may occur with the logical operations of the circuit. With this said, the new direction in the technology is headed towards programmable VDD states. Looking at one possible proposal for programmable implementation, one could have three states of operation: high VDD, low VDD, and power-gating. The high VDD state would be reserved for critical paths and the others to the non critical paths (Reference Publication Li, Lin, He, UCLA). This technology will greatly increase the ‘lifetime’ of any confined power source as unneeded draws and excess dissipation would be largely eliminated. Should such a technology hit the mainstream, it would be easy to see how its potential for portable device powering could revolutionize the industry. An additional benefit to VDD reduction also comes in improved power delay products.

 


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